1. FIELD OF THE INVENTION
The present invention relates to a vector processor which can efficiently supply data from a main storage to a processor to efficiently perform a vector operation.
2. DESCRIPTION OF THE RELATED ART
As the development of computers in a data processing field advances, various vector computer systems have been developed to improve a processing capability for vector data. Examples of such systems are those disclosed in U.S. Pat. Nos. 4,172,287 and 4,128,880. In the computer system disclosed in U.S. Pat. No. 4,172,287, a data transfer capability from a main storage to an operation unit, which fits to a performance of the operation unit, is required. However, there is a limit in the data transfer capability. In U.S. Pat. No. 4,128,880, in order to reduce a burden to the data transfer from the main storage, vector registers which hold vector data transferred from the main storage or interium results of the vector operation are arranged closer to the operation unit than to the main storage. The vector registers are effective means to efficiently operate a pipeline operation unit which processes the vector data. When the number of vector data necessary in one run of vector processing is smaller than the number of vector registers, the operation can be performed among the vector registers once the vector data have been loaded to the vector registers from the main storage. Accordingly, the effect of the vector register is significant. However, when the number of vector data necessary in one run of vector processing is larger than the number of vector registers, the transfer of the vector data between the main storage and the vector registers is necessary in the course of the vector processing. This is a big factor to degrade the performance.
In a general purpose large scale computer system, a cache memory is used to reduce a burden of data transfer between the registers and the main storage. Since the cache memory is primarily designed for scalar data, reference keys therefor are addresses and a holding unit is a block containing necessary data (for example, 64 contiguous bytes). Accordingly, it is difficult to use the cache memory between the main storage and the vector registers because (1) each data has to be referenced by an address, and (2) when non-contiguous vector data are to be handled, the cache memory contains many unuseful data.